This Data Stream Engine carries three data buffers that split the processing into sorting, computing and data-view phases for pipeline processing. A 32-bit wide data bus is used for communication with the acquisition memory and data processing memory. This architecture enables the DL7100 to maintain a high-speed screen update rate with long memory and multi-channel waveform display. The DL7100 can maintain a display update rate of 30 displays/sec even with 1 Mword of memory.
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